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1 5328a?image?05/03 features ? full-frame image sensor 4096 x 4096 pixels ? 11 m x 11 m photo-mos pixel with 100% aperture ? image zone: 45 x 45 mm ? frame readout through one, two or four outputs ? data rates up to 4 x 40 mhz (compatibility with 7, 4 frames/second) ? true 12-bit high dynamic range ? very low readout noise ? very low dark current (mpp mode) ? optimized resolution and responsivity in the 400 - 1100 nm spectrum ? on-chip thermometer for each quarter ? additional full-frame operating modes: ? 4/3 aspect ratio: 4096 x 3072 ? 2/1 aspect ratio: 4096 x 2048 ? binning 2 x 2 pixels (format 2048 x 2048 pixels of 22 x 22 m) ? binning 4 x 4 pixels (format 1024x 1024 pixels of 44 x 44 m) ? on-request frame transfer architecture: ? 2048 active lines, one memory zone with frame readout through one or two outputs ? 2048 active lines, two memories zones with frame readout through two or four outputs applications flexibility and performance make s this device suitable for di gital photography, graphic arts, medical or industrial applications and scientific analysis. description atmel's AT71201M is a full-frame sensor based on charge-coupled device (ccd) technology. it can be used in a wide range of applications thanks to operating mode flexibility, very high defini tion and high dynamic range. the nominal photosensitive area is made up of 4096 x 4096 useful pixels and is split into four independent zones that are driven separately by four independent four-phase clock sets. thus the sensor can be used in up to 12 main modes. the large format and high definition make the device suitable for any application requiring precision. the high sensitivity of the 11 x 11 m pixels with 100% fill factor provides a large bandwidth of response with up to 1100 nm wavelength. two serial registers and four independent output amplifiers offer a high-frequency functionality at 40 msps and up to 7.4 fram es per second with a high signal to noise ratio. 16 m-pixels sensor AT71201M preliminary rev. 5328a?image?05/03
2 AT71201M 5328a?image?05/03 pinout figure 1. AT71201M pinout, top view of the sensor abcdef ghj kl mnpqrst uvw x x 25 vss3 phir1 vdd1 vgs1 vthl1 vss2 phila8 phila7 vdea phipb2 phipa2 phipa4 phipb4 phifca phila3 phila4 vde vthl2 vgs2 vdd2 phir2 25 24 vdr1 vs1 vos1 phils1 vthh1 phila6 phila5 phita vss2 phipb1 phipa1 phipa3 phipb3 vss2 vss1 phila1 phila2 vthh2 phils2 vos2 vs2 24 register a at71201 register b 2 vdr3 vs3 vos3 phils3 vthh3 philb2 philb1 vss1 vss2 phipc3 phipd3 phipd1 phipc1 vss2 phitb philb5 philb6 vthh4 phils4 vos4 vs4 2 1 vss2 phir3 vdd3 vgs3 vthl3 vde philb4 philb3 phifcb phipc4 phipd4 phipd2 phipc2 vdeb philb7 philb8 vss2 vthl4 vgs4 vdd4 phir4 1 abcdef ghj kl mnpqrst uv w vss3 vdr2 vdr4 vss2 a zone b zone c zone d zone output 1 output 2 output 3 output 4
3 AT71201M 5328a?image?05/03 table 1. AT71201M pinout signal name parameter phila [1;8] registers a clocks philb [1;8] registers b clocks phils [1;4] summing clocks phir [1;4] reset gates phipa [1;4] image zone a clocks phipb [1;4] image zone b clocks phipc [1;4] image zone c clocks phipd [1;4] image zone d clocks phita image zone to register a transfer clock vgs [1;4] register output gate biases vos [1;4] video outputs vdd [1;4] amplifier drains vs [1;4] amplifier sources vdr [1;4] reset drains vde (2) peripheral vertical drain vdea peripheral drain along register a vdeb peripheral drain along register b vthl [1;4] thermometer low 1 to 4 vthh [1;4] thermometer high 1 to 4 vss (12) ground connection
4 AT71201M 5328a?image?05/03 block diagram figure 2. AT71201M block diagram - top view 4096 x 4096 useful pixels (11 x 11 m2) = 45 x 45 mm2 8 vertical & horizontal insulating elements (including 4 dark ones) 24 vertical references paj pbj pcj pdj paj pbj pcj pdj la1 to 4 lb1 to 4 ta tb ls1 vs1 vgs1 vos1 r1 vdd1 vdr1 vthh1 vthl1 ls3 vs3 vgs3 vos3 r3 vdd3 vdr3 ls4 vgs4 r4 vdr4 vthh3 vthl3 vs4 vos4 vdd4 vthh4 vthl4 vs2 ls2 vos2 vgs2 vdd2 r2 vthh2 vdr2 vthl2 la5 to 8 lb5 to 8 readout modes thermometer vdeb vdea vde vde 16 prescans a zone b zone c zone d zone } } } }
5 AT71201M 5328a?image?05/03 architectural overview general parameters notes: 1. the full-frame version can be read through one, two or four outputs 2. the lines summation into the register is made by a specific timing diagram. the inte- gration time should be adapted to prevent charge overflow. a specific clock allows column summation. the pixel size is 11 x 11m 2 with 100% fill factor (photo-mos technology). the sensor is compatible with a 180 rotation. the image zone commands are split in 4 horizontal areas. the combination of the pij clocks allows various transfer configurations. the serial registers are driven by 8 li clocks. an adapted combination of them allows transfers of 100% of stages to the right side or the left side or 50% in each direction. table 2. general parameters parameter value pixel size 11 x 11 m2 number of useful pixels per line 4096 number of useful lines 4096 number of extra lines 8 per register number of readout registers 2 number of prescan ccd stages (per output) 16 number of dark references (cells per line) 24 number of outputs (2 per register) 4 (1) mpp mode/low dark current mode yes (image zone) anti-blooming functionality no binning (summation) mode yes (2) pixel clocking mode 4-phase readout register clocking mode 2-phase specific functions thermometer
6 AT71201M 5328a?image?05/03 organization top to bottom the AT71201M is made up of four zones (a, b, c and d) that are separately driven. corner to center output amplifiers the charge packets are clocked towards t he output nodes and are converted to volt- ages. the potential at the output node is read through a source follower amplifier. figure 3. on-chip output amplifiers table 3. vertical characteristics zone configuration a 8 dummy lines (4 photosensitive ones) 2048 active lines, 100% photosensitive b 2048 active lines, 100% photosensitive c 2048 active lines, 100% photosensitive d 2048 active lines, 100% photosensitive 8 dummy lines (4 photosensitive ones) table 4. horizontal characteristics for different modes characteristic readout mode one output two outputs on same register prescan stages 16 16 dark references 24 24 insulating elements 8 8 useful pixels 4096 2048 m2 m1 m5 m4 m3 vos vdd vs m6 output node r
7 AT71201M 5328a?image?05/03 absolute maximum ratings (1) note: 1. stresses above those listed under absolute maximum rati ngs may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maxi mum ratings for extended periods may affect device reliability. table 5. maximum applied voltages with respect to vss signal name parameter min max phila [1;8] registers a clocks -0.3v +15v philb [1;8] registers b clocks -0.3v +15v phils [1;4] summing clocks -0.3v +15v phir [1;4] reset gates -0.3v +15v phipa [1;4] image zone a clocks -15v & phipa [others] -15v +15v & phipa [others] +15v phipb [1;4] image zone b clocks -15v & phipb [others] -15v +15v & phipb [others] +15v phipc [1;4] image zone c clocks -15v & phipc [others] -15v +15v & phipc [others] +15v phipd [1;4] image zone d clocks -15v & phipd [others] -15v +15v & phipd [others] +15v phita image zone to register a transfer clock -15v & phipa [4] -15v +15v & phipa [4] +15v phitb image zone to register b transfer clock -15v & phipb [4] -15v +15v & phipb [4] +15v vgs [1;4] ouput gates -0.3v +15v vos [1;4] video outputs -0.3v +15v vdd [1;4] amplifier drains -0.3v +15v vs [1;4] amplifier sources -0.3v +15v vdr [1;4] reset drains -0.3v +15v vde peripheral drain -0.3v +15v vdea peripheral drain along register a -0.3v +15v vdeb peripheral drain along register b -0.3v +15v vthl [1;4] thermometer low 1 to 4 -0.3v +15v vthh [1;4] thermometer high 1 to 4 -0.3v +15v vss ground
8 AT71201M 5328a?image?05/03 shorting vos to any other pin, even temporally, can permanently damage the output amplifier. device exposure to esd stress could result in current leakage or performance degrada- tion; reliability can also be affected. to avoid degradation, sensors (including pins and package) have to be handled care- fully using a grounded bracelet. when unplugged, they have to be stored in the original case (or box). in any case, pins of the devices must not be discharged straight to ground.. dc characteristics notes: 1. if the associated output i is not used, vddi should be st ated to 0 volts in order to reduce global power consumption 2. vdri voltage should always be kept lower than vddi voltage, especially during power on recommendation: all dc voltages should be bypassed by adding capacitors as closed as possible to the pin connection. storage temperature range -40 c to +70 c operating temperature range 0 c to +70 c thermal cycling 3 c/mn table 6. dc characteristics parameters symbol typical value adjusting range current source bias vsi 0v [0;1] volts 4 x -25 ma amplifier drain supply vddi (1) 15v [14.5;15.5] volts 4 x 25 ma substrate bias vss 0v reset diode vdri (2) 14v [13.5;14.5] volts < 5 a output gate vgsi 3.5v [3;4] volts < 5 a vertical drain vde 8v [6;9] volts (15 v max respect to ti) < 50 a horizontal drain vdei 12v [6;15] volts < 50 a
9 AT71201M 5328a?image?05/03 drive clock characteristics notes: 1. i = a to d, j = 1 to 4 2. k = a to b, m = 1 to 8 table 7. drive clock characteristics parameter symbol state minimum typical maximum typical capacitance image clocks phip ij (1) low -9v -8v -7.5v 37 nf high +2.5v +3v +3.5v transfer clocks phit k (2) low -6v -5v -4v 200 pf high +2.5v +3v +3.5v register clocks phil km (2) low 0v 0v 0.5v 180 pf high +7v +7.5v +8v summing clocks phils j (1) low 0v 0v 0.5v 15 pf high +7v +7.5v +8v reset gate clocks phir j (1) low 0v +2v +3v 15 pf high +11v +12v +13v
10 AT71201M 5328a?image?05/03 operating modes for the required readout mode, the vertical a nd horizontal clocks must be tied together, as following: figure 4. operating modes pa1= pb1= pc1= pd1= p1 pa4= pb4= pc2= pd2= p2 pa3= pb3= pc3= pd3= p3 pa2= pb2= pc4= pd4= p4 pa1= pb1= pc1= pd1= p1 pa2= pb2= pc4= pd4= p2 pa3= pb3= pc3= pd3= p3 pa4= pb4= pc2= pd2= p4 pa1= pb1= pc1= pd1= p1 pa2= pb2= pc2= pd2= p2 pa3= pb3= pc3= pd3= p3 pa4= pb4= pc4= pd4= p4 pa1= pb1= pc1= pd1= p1 pa2= pb4= pc2= pd2= p2 pa3= pb3= pc3= pd3= p3 pa4= pb2= pc4= pd4= p4 12121 2 mode1 mode4 mode7 mode10 3 43 43 43 4 121 21 21 2 mode2 mode5 mode8 mode11 343 43 43 4 1 21 21 21 2 mode3 mode6 mode9 mode12 343 43 43 4 vertical transfer 4112 transfers min nbv = 4112 4112 transfers min nbv = 4112 3080 transfers min nbv = 3080 2056 transfers min nbv = 2056 1-2-3 modes 4-5-6 modes 7-8-9 modes 10-11-12 modes ta = low level tb = p1 ta = p1 tb = low level ta = p1 tb = p1 ta = p1 tb = p1 1 inactive inactive inactive 2 inactive inactive inactive 4144 pixels periods nbh = 4144 4144 pixels periods nbh = 4144 2096 pixels periods nbh = 2096 horizontal transfer la1= la4= la5= la7= l1 la2= la3= la6= la8= l2 lb1= lb3= lb5= lb8= l1 lb2= lb4= lb6= lb7= l2 lb1= lb4= lb5= lb7= l1 lb2= lb3= lb6= lb8= l2 la1= la3= la5= la8= l1 la2= la4= la6= la7= l2 lb1= lb3= lb5= lb7 = l1 lb2= lb4= lb6= lb8= l2 la1= la4= la5= la8= l1 la2= la3= la6= la7= l2 6-9-12 modes 2-8-11 modes 5-8-11 modes 1-7-10 modes 4-7-10 modes 3-9-12 modes symbols p1, p2, p3, p4 correspond to the clocks described in the full-frame mode timing diagrams. abbreviations nbv and nbh correspond respectively to the vertical and horizontal number of transfers. the unused horizontal clocks ( l, r, ls) must be stated to their higher level.
11 AT71201M 5328a?image?05/03 timing diagrams figure 5. full-frame mode timing diagram figure 6. line timing diagram notes: 1. t0 = master clock period (vertical transfer) 2. see figure 4 phip1 phip2 phip3 phitk phil1 phil2 philsj phirj phip4 nbh pulses ... cleaning cleaning ... integration time readout time (nbv pulses) (2) (2) period tv = 9 x t0 phip1 phip2 phip3 phip4 phitk = phip1 phil1 phil2 philsj phirj (2) (2) (1)
12 AT71201M 5328a?image?05/03 figure 7. summation timing diagram of 2 lines figure 8. readout signal notes: 1. t0 = master clock period (vertical transfer) 2. see figure 4 3. fh = readout register frequency phip1 phip2 phip3 phip4 phitk = phip1 phil1 phil2 philsj phirj period tv = 15 x t0 line summation (2) (2) (1) phip1 phip2 phip3 phip4 phitk phil1 phil2 philsj phirj vosj reset/reference/signal levels period = fh -1 (2) (2) (3)
13 AT71201M 5328a?image?05/03 figure 9. summation timing diagram note: 1. see figure 4 figure 10. frame transfer sequence the readout sequence corresponding to an image made of c x l pixels ? xc = 2048 in modes 3, 6, 9, 12 ? xc = 4096 in other modes ? yl = 2048 in modes 1 to 6 ? yl = 4096 in modes 7 to 9 phip1 phip2 phip3 phip4 phitk phil1 phil2 philsj phirj vosj (1) (1) column summation reset/reference/signal levels yes readout time exposure time l-1 times 1 line transfer x columns summation y lines summation 1 stage transfer cleaning period yes lines summation columns summation c-1 times (y-1) times (x-1) times
14 AT71201M 5328a?image?05/03 t0 = master clock perio d (vertical transfer) frame rate characteristics figure 11. frame rate characteristics frame rate is given for maximum readout frequency (1) . note: 1. horizontal pixel frequency, fh = 40 mhz vertical transfer time, to = 1.5 s buffer time, tb = 100 ns table 8. time constants of different phases time symbol minimum typical maximum buffer time = waiting time between p ij and l km acting tb 100 ns - - rise time and fall time of p ij, t k ts 250 ns 0.5 x t0 0.5 x t0 rise time and fall time of l km, ls j tq 3 ns 6 ns - rise time and fall time of rj tr 1.5 ns 3 ns - 0 2 4 6 8 10 12 14 020406080100 integration time (ms) frame/sec 1 output 2 output 4 output 4 outputs (2 x 2 binning)
15 AT71201M 5328a?image?05/03 output buffer note: 1. per output 2. all characteristics given for temperature = 25 c electro-optical performances notes: 1. combined with 2 mm "bg38" ir filter type 2. standard deviation 3. all values given at 25 c, typical voltages table 9. output buffer (2) parameter symbol minimum typical maximum unit dc output vref 8.0 8.6 9.2 v output impedance zout ? 88 ? ? output amplifier supply current (1) idd 19 25 31 ma amplifier bandwidth (-3 db) bw ? 200 ? mhz charge to voltage conversion factor cvf ? 6.0 ? v/ electron temperature conversion vth ? 7.5 ? mv/ c vertical transfer time t0 1.5 2 ? s readout register frequency fh ? ? 40 mhz table 10. electro-optical performances (3) parameter symbol minimum typical maximum unit pixel saturation voltage vsat 600 750 900 mv readout saturation charge in binning mode rsat ? 1800 ? mv dynamic range dr 72 74 76 db readout noise rn ? 25 ? electron responsivity r 3.8 4.2 ? v/(j/cm2) resolution (mtf) at 45 cycles/mm ? h axis resolution (mtf) at 45 cycles/mm ? v axis mtfx (1) mtfy (1) ? ? 45 50 ? ? % % pixel response non-uniformity prnu (1)(2) ? 0.5 3 % image zone dark signal, mpp image zone dark signal, non-mpp register dark signal, non-mpp ds1 ds2 dsr 0.05 10 30 0.2 20 60 2 40 100 mv/s mv/s mv/s image zone dark signal non-uniformity, mpp integration dsnu (2) ? 0.5 1.5 mv/s horizontal charge transfer efficiency per ccd stage hcte 0.99993 0.99998 ? ? vertical charge transfer efficiency per ccd stage vcte 0.99995 0.99998 ? ?
16 AT71201M 5328a?image?05/03 figure 12. spectral responsivity temperature measurement a current of 100 a is fo rced between vthli and vthhi, in the range of 0 to 70 c, the corresponding measured voltage, is proportional to temperature: relative thermometer accuracy is 0.13 c/mv 10% absolute thermomete r precision is 10 c. figure 13. on chip thermometer 14 12 10 8 6 4 2 0 400 500 600 700 800 900 1000 1100 wavelength (nm) responsivity (v/ j/cm2) ) ( 613 ) / ( 5 . 7 ) ( ) ( ) ( c c mv mv vthli mv vthhi c e temperatur ? ? = vthhi vthli i forced resistor
17 AT71201M 5328a?image?05/03 image grade notes: 1. d-min: distance of pixels defects in any direction. all occurrences are non-contiguous. 2. testing has been carried out under the following conditions: operating temperature = 25 c illumination conditions: 3200k halogen lamp wit h bg38 infrared filter and f/3.5 aperture integration time in darkness = 10 seconds, test under illumination at 50% of vsat standard mode, to = 1.5 s, fh = 40 mhz definitions table 11. image grade (2) grade blemishes cluster 1 cluster 2 column total d-min (1) total d-min (1) total d-min (1) total d-min (1) e 1500 3 100 50 20 100 10 150 table 12. defect sizes type description blemish 1 x 1 pixel defect cluster blemish groupings of less than a given number of adjacent defects: 1 x 1 pixel < cluster 1 size 2 x 2 pixels 2 x 2 pixels < cluster 2 size 5 x 5 pixels column one-pixel-wide column with more than seven contiguous defective pixels table 13. defects in darkness type description blemish/clusters pixel signal deviation of more than 200 mv from the average output signal column column signal deviation of more than 50 mv from the average output signal table 14. defects under illumination type description blemish/clusters pixel signal deviation of more than 30% from the average output signal column column signal deviation of more th an 20% from the average output signal
18 AT71201M 5328a?image?05/03 ordering information the following part numbers are available: ? AT71201Mcrer ? AT71201Mcren 1234567891011 at71201 technological variant temperature range: c: 0c to +70c package family: r: pin grid array (pga) image grade: e: standard h: high customer specification quality assurance level options: b = mechanical mask e = on chip color filters package variant: n: non-sealed window r: anti-reflective glass window
19 AT71201M 5328a?image?05/03 package drawing 71.00 0.8 61.80 0.7 55.80 0.6 35.5 0.4 6. 68.0 0.7 6. 1.00 0.01 54.0 0.5 x = 12.970 0.2 8.5 0.8 5. 6. y = 12.970 0.2 35.5 0.4 6. reference (ring) zopt. = 1.1 0.08 zmech. = 0.7 0.05 (see note 3. - 4.) 4.57 0.25 2. 1.1 0.1 (window) 2.06 0.2 2.5 0.25 53.34 0.55 2.54 typ. 2.54 typ. 1 2 notes: 1. anti-reflective window 400 - 700 nm 2. photosensitive area 3. zopt = optical distance between reference surface and 2 4. zmech = mechanical distance between reference surface and 2 5. pin a1 index mark 6. mechanical references/die positionning (first pixel) reference: z reference: xy all dimensions in millimeter 24 25 60.96 0.6 55.88 0.6 abcdef ghj kl mn pqrs tuvwx 1. 0.46 0.05 5.66 0.5 5. first pixel die flatness 50 m die axis angle 0.2
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